µModule H-Bridge module

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Preliminary information: Documentation is not fully updated

Introduction

This µModule implements a 20A H-bridge with rich feed-back options to create a closed-loop speed-controller application. The module interfaces to the external world using the TWI interface that's common among all µModules. It also has an optional CMOS-level RS-232 interface option. It can control motors up to 18V.

Features

Standard µModule TWI with optional RS-232 interface
Integrated 3.3V power supply, 5V operation is optional usnig an external power source
20A current limit
7 to 18V motor voltage
High-side short-circuit protection
High efficiency n-channel MOSFETs
Rich speed-feedback options for closed-loop operation
Back-EMF feedback for sensorless motion-control
PID control loop
Acceleration and deceleration limits
Travelled distance calculation
'Go-to-distance' support with trapesiod speed-profile
Braking and free-wheeling support
Parameters can be stored in permanent EEPROM storage
Dity-cycle throttling to limit throttle

License

This document and all the accompanying design documentation (for example schematic and PCB files) are covered by the H-Storm Non-Commercial License (HSNCL).

H-Storm Non-Commercial License (HSNCL)

Redistribution and use in source or binary forms, or incorporated into a physical (hardware) product, with or without modification, are permitted for non-commercial use only, provided that the following conditions are met:

The redistribution doesn't result in financial gain.
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in any other form must contain in printed or electronical format the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
All advertising materials mentioning features or use of this technology must display the following acknowledgment:
This product includes H-Storm technology developed by Andras Tantos and Modular Circuits.
Neither the name of Andras Tantos or Modular Circuits may be used to endorse or promote products derived from or using this technology without specific prior written permission.

ALL THE INFORMATION, TECHNOLOGY, AND SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANDRAS TANTOS, MODULAR CIRCUITS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE OR TECHNOLOGY, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Design description

The bus interface

The TWI bus interface follows the µModule standards. There are two four-pin telephone sockets on the board, both with identical functionality. The two center wires are used for the TWI signal transmission (clock and data) while the other two provide power and ground signals. The interface can be operated at a rate up to 400kHz. This module never initiates any transactions on the bus, it operates in slave-only mode. Status information can be acquired by polling and commands can be sent to the module at any time. The module implements the H-Storm PnP command set with extentions specific to the function of the module.

Powering options

The module can source and sink power on this interface. The power to and from these sockets can be interrupted by an on-board jumper. With this there are three possible powering configurations with regards to the logic-level functions:

The module is powered form the same power supply as the motor. The module provides power to other devices on the TWI bus
The module is powered from the power supply of the motor however it does not power other devices on the TWI bus
The module is powered from the TWI bus

The third powering mode has to be used if 5V operation is required.

The H-bridge

The H-bridge is comprised from 4 n-channel power MOSFETs. These transistors have extremly low on-resistance, leading to high-efficiency and low heat-generation even at high power levels. By replacing the standard IRFZ48 transistors with IRL2203 ones, no heat-sink is required up to 10A of continous current. The efficiency of the bridge is almost 98% from a 18V supply, 96% at 10V and 94.7% at 7.2V supply voltage. The transistors are driven by LTC1155 dual-channel high-side driver ICs. These devices can deliver higher gate control voltages than the power supply thus allowing the use of n-channel MOSFETs on the high-side of the bridge as well. These chips also provide a second level of short-circuit protection by measuring the voltage drop on the sense resistor. Shot-through protection is established by monitoring the low-side gate voltage and disabling the high-side gate drives until the low-side gate voltage drops low enough. This mechanism also provides protection agains opening a low and a high-side driver of the same half of the bridge at the same time. Since the drivers can provide significantly higher voltages (especially for the low-side MOSFETs) than the maximum allowable GS voltage, a zenner protection diode limits the GS voltage to 10V. All four MOSFETs can independently be turned on and off (with the exception of two MOSFETs on the same side being turned on at the same time) allowing all possible valid operating modes of the bridge to be used:

Forward drive
Backward drive
Free-wheeling
Braking

Feedback options

A wide range of feedback options are available on the module to provide additional health-monitoring and establishing closed-loop speed-control functionality. Both voltage (relative to the ground) on the motor connectors can be monitored as well as the voltage across the current-sense resistor which is proportional to the current flowing through the motor. Monitoring these values with a 10-bit resolution A/D converter precise knowledge of the current system status can be established. These measurements can be used to calculate the back-EMF response of the driven motor, which is proprotional to the rotation speed. This value in turn can be used to colse the control loop and create a true speed-controlled H-bridge. When more precise measurement of the rotation is required, an external quadrature encoder can be used and the signal of the optical gates can be fed back to the module. Two input pins are wired to a header for that purpose.

Miscelanious functions

The module on the top of the standard TWI interface, that is commond among all µModules also contains a (logical level) RS-232 interface as well. This interface can be used to connect the module to other microcontroller modules or (after level-shifting) to a PC which doesn't have a TWI interface.

Plug-and-play Address Assignment Protocol

The PnP protocol allows the discovery of µModules attached to a single I²C bus and the assignment of soft-addresses to them. This soft-address is later used to select one of the many µModules on the system. After this soft-address is assigned to a module, it will respond to regular I²C commands on the bus, which contain that address. It is the responsibility of the master who does the enumeration of the modules on the bus to make sure that every module is assigned a unique soft-address that's not in conflict with any other address on the bus. This protocol allows the use of multiple identical µModules on the same bus.

The PnP protocol uses standard I²C commands over the bus and does not interfere with regular non-PnP capable devices on the same bus as long as none of those non-PnP devices answer the general-call address (address 0).

The following discussion uses I²C bus terminology. Please refer to the I²C specification for details.

Command syntax

Every PnP command consists of a start bit, an address - which is always the general call address - and the read/write bit, one or more data bytes, and a stop or re-start bit. Between each byte of transmission there's an acknowledge bit. The acknowledge bit is generated by the receiving partner(s) of the previously transmitted byte. A positive acknowledge is a logical '0', a negative acknowledge is a logical '1'.

All PnP command uses the general call address, which is 0. The first byte of the transaction therefore is 0x00 for write and 0x01 for read operations. If there is a PnP-capable device on the bus, all of them will acknowledge the address. If the master receives a NACK for the address-byte it can assume that there are no PnP capable devices on the bus. If the first byte identifies a write transaction, the master continues sending bytes until the transaction is finished with a stop or re-start bit. If the first byte identifies a read transaction, the addressed device(s) will transmit data to the master, until it terminates the transaction with a stop or re-start bit. A write transaction can be terminated early if the last byte was not acknowledged byte the receiver(s). A read transaction can also be terminated by a negative acknowledge. Furthermore the last byte of a read transaction should always be negatively acknowledged by the master.

For write operations, the first byte after the address byte identifies the command that is sent to the device. Additional bytes in the command may follow and their meaning depends on the command code.

The layout of a write command is the following:

Bit location	S	7	6	5	4	3	2	1	0	Ack	7	6	5	4	3	2	1	0	Ack	7	6	5	4	3	2	1	0	Ack	...	P
Meaning		General call address (0)							R/W (0)	0	Command code								0	Command-dependent data (if any)								0	...

Note: gray bits are driven by the slave(s), white bits are driven by the master.

If the first byte spesifies a read command, PnP-capable devices start sending information to the master. The information sent depends on the last received write command code. Note that at this point more than one PnP-capable device might start sending information to the master at the same time. The I²C bus arbitration protocol is used by the competing devices to decide the ownership of the bus. It is guaranteed that the data that is received by the master will be consistent and by the end of the communication there's only one PnP-capable device left on the bus.

The layout of a read command is the following:

Bit location	S	7	6	5	4	3	2	1	0	Ack	7	6	5	4	3	2	1	0	Ack	...	7	6	5	4	3	2	1	0	Ack	P
Meaning		General call address (0)							R/W (1)	0	First byte								0	...	Last byte								1

The `ResetDevice` Command

This command is received by all PnP-capable devices independent of wether they have an already assigned soft-address or not. This command clears the soft-address if there is one already assigned, and resets the device PnP subsystem inside the device to its defult state. After reception of this command the device will not answer to any transaction on the I²C bus other than PnP protocol commands. Other functionality of the device may or may not be affected.

The command doesn't have any additional bytes after the command code. All PnP-capable devices are required to acknowledge this command.

Bit location	S	7	6	5	4	3	2	1	0	Ack	7	6	5	4	3	2	1	0	Ack	P
Meaning		General call address (0)							R/W (0)	0	Reset Device Command (1)								0

The `GetConfig` Command

This command is interpreted only by those PnP-capable devices that don't have a valid soft-address assigned to them. The command is used to get the parameter record of the PnP-capable devices. The command itself has no additional parameters but should be followed immediately by a read transaction.

Bit location	S	7	6	5	4	3	2	1	0	Ack	7	6	5	4	3	2	1	0	Ack
Meaning		General call address (0)							R/W (0)	0	Reset Device Command (1)								0

S	7	6	5	4	3	2	1	0	Ack	7	6	5	4	3	2	1	0	Ack	...	7	6	5	4	3	2	1	0	Ack	P
	General call address (0)							R/W (1)	0	First byte of the parameter record								0	...	Last byte of the parameter record								1

The `AssignAddress` Command

Design files

Schematic and PCB in PDF format (HSNCL)
Firmware source code (HSNCL)